1. Field of the Invention
This invention relates to an input/output (I/O) interface circuitry for high speed integrated circuit (IC) applications. More specifically, it relates to the low voltage differential signaling input buffers that have a wide common mode input range and low power consumption.
2. Description of the Related Art
Differential drivers and receivers are well known. Differential drivers and receivers are used in many input/output (I/O) applications such as in communications, video and integrated circuits that may demand high data transfer rate. Differential drivers and receivers are used in integrated circuits (IC) for on-chip communications between circuits, chip-to-board, off-chip communications, etc.
Low-voltage differential signaling (LVDS) technology was developed in order to provide a low-power and low-voltage alternative to other high-speed I/O interfaces specifically for point-to-point transmissions, such as those used in a network devices within data and communication networks. LVDS can be implemented in IC's to overcome some deficiencies with previous I/O interface circuitry.
In conventional I/O designs, high-speed data rates are accomplished with parallel I/O structures, where each I/O device typically has a limited bandwidth. As bandwidth is increased, more I/O devices are required to achieve the increased bandwidth. Over the years, bandwidth has increased substantially leading to massive parallelism in I/O designs in IC's and require more power. As a result, these parallel I/O structures occupy more and more space on IC's. This complicates the design of the circuits because there is less space available on the chip and increases the cost of such IC's because of the additional power required because of the numerous extra pads, current sources, etc. necessary in a parallel structure. Thus, most existing I/O drivers are not power efficient.
LVDS interfaces have reduced voltage swing and can operate at very high speed with less power consumption. With differential outputs, a LVDS receiver can reject ambient common mode noise and less parallelism is needed due to the increased data rate of LVDS I/O drivers. Thus, the use of LVDS can reduce the overall cost and size of high speed ICs.
However, LVDS requires a common mode input voltage that is substantially bounded by the supply voltages. This is often referred to as a rail-to-rail input voltage. In Complementary Metal-Oxide-Semiconductor (CMOS) process, two types of transistors are available for the IC design: N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS). An NMOS transistor is turned ON when the gate voltage (Vg) is above the source voltage (Vs) by the threshold voltage (Vtn), or when Vg−Vs>Vtn. Since Vs is typically set to ground, to turn an NMOS transistor ON, it is required to have Vg>Vtn. If Vtn is in a range of 0.4V, the transistor will be OFF if the input Vg is near ground.
A PMOS transistor is turned ON when the gate voltage is below the source voltage (Vs) by threshold voltage (Vtp), or when Vs−Vg>Vtp. Vs is typically the power supply voltage, VDD. Thus to turn a PMOS transistor ON, it is required to have Vg<VDD−Vtp. If Vtp is in a range of 0.4V, the PMOS transistor will be OFF if Vg=VDD, since Vg>VDD−0.4. Therefore, neither an NMOS nor a PMOS input stage can meet a rail-to-rail common-mode input range 0V<V<2.4V, which is specified by the LVDS standard, in IEEE Std. 1596.3-1996.
A prior art wide input range amplifier is shown in FIG. 5. The amplifier includes two input buffers B1 and B2, which may be implemented by a PMOS stage and an NMOS stage. The outputs of buffers B1 and B2 are combined in a MUX M1, which receives an input control signal from a Schmidtt trigger ANDed with the common mode voltage Vcm, via a third buffer B3. The control signal Z selects which output range to use, XP or XN. This is then input into the digital logic of the circuit.
This prior art design is complicated and takes up much space on the chip. Furthermore, the prior art design increases power consumption necessary, therefore increasing the cost of the chip or IC.
In view of the deficiencies in the prior art, there is a need for new and improved systems and methods for buffering LVDS in modern I/O applications.